The invention relates to a method for fabricating a field-effect transistor having an anti-punch-through implantation region. The invention also relates an improved transistor structure for DRAM one-transistor memory cells having feature sizes of less than 0.15 xcexcm.
When fabricating large-scale integrated memory devices such as DRAM memories, it becomes increasingly difficult, with feature sizes or structure sizes of less than 0.15 xcexcm, to produce transistors having not only an excellent leakage current behavior with Ioff less than 10 fA (fF) per transistor, which is essential for the charge retention time, or retention time, in a one-transistor memory cell but it becomes also difficult to produce transistors having a sufficient ON current for charge storage of  greater than 30 xcexcA per transistor. At the same time, it is desirable to realize low threshold voltages of approximately 0.8 V in conjunction with an external voltage supply of just 1.6 V, for example.
FIGS. 1a and 1b show a simplified sectional view of essential method steps for fabricating a field-effect transistor having an anti-punch-through implantation region in accordance with the prior art, as is disclosed for example in U.S. Pat. No. 5,686,321.
Since the so-called punch-through effect is a major problem particularly when fabricating large-scale integrated field-effect transistors, anti-punch-through implantation regions are increasingly used, particularly in the case of short-channel transistors. These anti-punch-through implantation regions reduce an excessive expansion of a depletion region or space charge zone in the channel region and thereby increase a punch-through voltage.
By way of example, anti-punch-through implantation regions of this type are implanted in a self-aligning manner locally between respective source/drain regions, as a result of which feature sizes of xe2x89xa60.15 xcexcm can be realized.
In accordance with FIG. 1a, in such a conventional method for fabricating a field-effect transistor having an anti-punch-through implantation region, first of all a gate insulation layer 20 is formed over the whole area of a semiconductor substrate 10. Subsequently, a nitride layer 30 is deposited as a mask layer and patterned accordingly in order to form respective gate regions GB. Furthermore, polysilicon spacers 50 are formed on the edge regions of the cut-out for the gate region GB, and act as additional masking for the subsequent implantation I1. In this case, in the course of the implantation I1, using the polysilicon spacers 50 and the nitride mask layer 30, impurities are introduced locally into a channel region of the semiconductor substrate 10, thereby forming the anti-punch-through implantation region 40.
In accordance with FIG. 1b, in subsequent steps of the conventional method for fabricating a field-effect transistor having an anti-punch-through implantation region 40, the spacers 50 are removed and the cut-out for the gate region GB is filled with a gate layer in order to form a gate electrode or control electrode 60. Subsequently, the nitride mask layer 30 is removed and, using the gate electrode 60, a further implantation I2 is carried out in order to form source/drain regions S and D in the semiconductor substrate 10.
A field-effect transistor having improved short-channel properties which can be fabricated in a self-aligning manner is obtained in this way. A disadvantage of this conventional fabrication method, however, is in particular the use of additional method steps for forming the masking spacers 50 and the implantation through the gate insulation layer 20. The implantation through the gate insulation layer 20, in particular, can adversely effect the quality of the gate insulation layer, thereby impairing the transistor properties of the short-channel transistor.
It is accordingly an object of the invention to provide a method for fabricating a field-effect transistor having an anti-punch-through implantation region which overcomes the above-mentioned disadvantages of the heretofore-known methods of this general type and which can be realized cost-effectively and yields improved transistor properties in combination with reduced feature sizes.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating a field-effect transistor having an anti-punch-through implantation region, the method includes the steps of:
forming a mask layer on a surface of a semiconductor substrate;
selectively removing a given region of the mask layer for forming a gate region;
forming an implantation mask layer on a surface of the mask layer in a region including the gate region;
forming an anti-punch-through implantation region in the semiconductor substrate at the gate region by implanting impurities;
removing the implantation mask layer;
forming, at the gate region, a gate insulation layer on the surface of the semiconductor substrate;
forming a gate layer in the gate region;
removing the mask layer; and
forming source/drain regions in the semiconductor substrate by using the gate layer as a mask.
In other words, the method according to the invention includes the following steps:
a) formation of a mask layer on the surface of a semiconductor substrate;
b) selective removal of predetermined regions of the mask layer in order to form gate regions;
c) formation of an implantation mask layer on the surface of the mask layer with the gate regions;
d) implantation of impurities in order to form the anti-punch-through implantation region in the semiconductor substrate of the gate region;
e) whole-area removal of the implantation mask layer;
f) formation of a gate insulation layer on the surface of the semiconductor substrate in the gate region;
g) formation of a gate layer in the gate region;
h) removal of the mask layer; and
i) formation of source/drain regions in the semiconductor substrate using the gate layer as a mask.
As a result, in particular, of the formation of an implantation mask layer, which can be easily realized, for the formation of the anti-punch-through implantation region and the subsequent formation of a gate insulation layer, a short-channel field-effect transistor having improved properties is obtained since the gate insulation layer is spared the bombardment of impurities during an implantation.
The implantation mask layer is preferably produced by depositing a homogeneous insulating layer from the vapor phase, resulting in a particularly cost-effective method for forming the implantation mask layer, which, in particular, enables the reliable fabrication of planar transistors having a feature size of less than 0.1 xcexcm. As a result, it is possible to achieve a further reduction in a cell area of large-scale integrated one-transistor memory cells, such as e.g. in DRAMs. Also, an alternative solution which is complicated in terms of production engineering, such as e.g. vertical transistors, can be avoided.
The implantation of impurities for the purpose of forming the anti-punch-through implantation region is preferably effected vertically or in an oblique or inclined manner. Thus a local channel implantation for a central or a slightly offset channel region of the field-effect transistor is achieved through the use of self-aligning masking technology. In this way, it is possible to further reduce high local field strengths in source/drain regions and to realize high saturation currents in the turned-on field-effect transistor.
According to another mode of the invention, an SiO2 layer is used as the implantation mask layer.
According to yet another mode of the invention, the gate insulation layer is formed by thermally oxidizing the semiconductor substrate.
According to a further mode of the invention, an SiO2 layer is used as the gate insulation layer.
According to another mode of the invention, weakly and heavily doped source/drain regions are formed. The heavily doped source/drain regions are formed by using spacers disposed laterally at the gate layer.
According to yet another mode of the invention, the step of forming the source drain regions includes implanting further impurities.
According to another mode of the invention, an Si3N4 hard mask is used as the mask layer.
According to a further mode of the invention, a polysilicon layer and/or a WSix layer is used as the gate layer.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for fabricating a field-effect transistor having an anti-punch-through implantation region, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.